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| 1/25 STLC3055N february 2006 1features monochip slic optimised for wll & voip applications implement all key features of the borsht function single supply (5.5 to 12v) built in dc/dc converter controller soft battery reversal with programmable transition time. on-hook transmission. programmable off-hook detector threshold metering pulse generation and filter integrated ringing integrated ring trip parallel control interface (3.3v logic level) programmable constant current feed surface mount package integrated thermal protection dual gain value option bcd iii s, 90v technology -40 to +85c operating range 2description the STLC3055N is a slic device specifically de- signed for wll (wireless local loop) and isdn- terminal adaptors and voip applications. one of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from +5.5v to +12v) and self generate the negative bat- tery by means of an on chip dc/dc converter con- troller that drives an external mos switch. wll & isdn-ta subscriber line interface circuit figure 2. block diagram pd d0 d1 d2 det rttx cac iltf rd iref rlim rth csvr cvcc vpos bgnd tip ring vbat agnd tx rx zac1 zac rs zb cttx1 cttx2 fttx ckttx supervision ttx proc ac proc reference stage line driver crev input logic and decoder output logic volt. vcc vss agnd output reg. status and functions clk rsense gate vf dc/dc conv. dc proc vbat gain setting rev. 10 fi gure 1. p ac k age table 1. order codes (*) ecopack? (see section 9 ) part number package STLC3055N tqfp44 e-STLC3055N (*) tqfp44 tqfp44
STLC3055N 2/25 2 description (continued) the battery level is properly adjusted depending on the operating mode. a useful characteristic for these applications is the integrated ringing generator. the control interface is a parallel type with open drain output and 3.3v logic levels. the metering pulses are generated on chip starting from two logic signals (0, 3.3v) one define the meter- ing pulse frequency and the other the metering pulse duration. an on chip circuit then provides the proper shaping and filtering. metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. a dedicated cancellation circuit avoid possible codec input saturation due to metering pulse echo. constant current feed can be set from 20ma to 40ma. off-hook detection threshold is programmable from 5ma to 9ma. the device, developed in bcdiiis technology (90v process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when t j exceeds 140c. figure 3. pin connection table 2. absolute maximum ratings (1) vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfil the a.m limits (see external components table page 10) symbol parameter value unit v pos positive supply voltage -0.4 to +13 v a/bgnd agnd to bgnd -1 to +1 v v dig pin d0, d1, d2, det , ckttx -0.4 to 5.5 v t j max. junction temperature 150 c v btot (1) vbtot=|vpos|+|vbat|. (total voltage applied to the device supply pins). 90 v esd rating human body model 1750 v charged device model 500 v 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 n.c. gain set pd d1 d0 d2 cttx2 cttx1 ckttx n.c. det rttx fttx rx zac1 rs zac zb cac tx vf clk vbat1 crev n.c. tip n.c. n.c. n.c. ring n.c. vbat bgnd rlim agnd cvcc rsense gate vpos csvr iltf rd iref rth d00tl488-mod 12 13 14 15 16 3/25 STLC3055N table 3. operating range (1) vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfil the a.m limits (see external components table page 11) table 4. thermal data table 5. pin description symbol parameter value unit v pos positive supply voltage 5.5 to +12 v a/bgnd agnd to bgnd -100 to +100 mv v dig pin d0, d1, d2, det , ckttx, pd -0.25 to 5.25 v t op ambient operating temperature range -40 to +85 c v bat (1) self generated battery voltage -74 max. v symbol parameter value unit r th j-amb thermal resistance junction to ambient typ. 60 c/w n pin function 1 d0 control interface: input bit 0. 2 d1 control interface: input bit 1. 3 d2 control interface: input bit 2. 4 pd power down input. normally connected to cvcc (or to logic level high). 5 gain set control gain interface: 0 level r xgain = 0db t xgain = -6db 1 level r xgain = +6db t xgain = -12db 6,7,36, 38,39,40,42 nc not connected. 8det logic interface output of the supervision detector (active low). 9 ckttx metering pulse clock input (12 khz or 16khz square wave). 10 cttx1 metering burst shaping external capacitor. 11 cttx2 metering burst shaping external capacitor. 12 rttx metering pulse cancellation buffer output. ttx filter network should be connected to this point. if not used should be left open. 13 fttx metering pulse buffer input this signal is sent to the line and used to perform ttx filtering. 14 rx 4 wire input port (rx input). a 100k ? external resistor must be connected to agnd to bias the input stage. this signal is referred to agnd. if connected to single supply codec output it must be dc decoupled with proper capacitor. 15 zac1 rx buffer output, (the ac impedance is connected from this node to zac). 16 zac ac impedance synthesis. 17 rs protection resistors image (the image resistor is connected from this node to zac). 18 zb balance network for 2 to 4 wire conversion (the balance impedance zb is connected from this node to agnd. za impedance is connected from this node to zac1). 19 cac ac feedback input, ac/dc split capacitor (cac). 20 tx 4 wire output port (tx output). the signal is referred to agnd. if connected to single supply codec input it must be dc decoupled with proper capacitor. 21 vf feedback input for dc/dc converter controller. STLC3055N 4/25 3 functional description the STLC3055N is a device specifically developed for wll voip and isdn-ta applications. it is based on a slic core, on purpose optimised for these applications, with the addition of a dc/dc con- verter controller to fulfil the wll and isdn-ta design requirements. the slic performs the standard feeding, signalling and transmission functions. it can be set in four different operating modes via the d0, d1, d2 pins of the control logic interface (0 to 3.3v logic levels). the loop status is carried out on the det pin (active low). the det pin is an open drain output to allow easy interfacing with both 3.3v and 5v logic levels. the four possible slic?s operating modes are: power down high impedance feeding (hi-z) active ringing 22 clk power switch controller clock (typ. 125khz). this pin can also be connected to cvcc or agnd. when the clk pin is connected to cvcc an auto-oscillation is internally generated and it is used instead of the external clock. when the clk pin is connected to agnd, the gate output is disabled. 23 gate driver for external power mos transistor (p-channel). 24 rsense voltage input for current sensing. rsense should be connected close to this pin and vpos pin. the pcb layout should minimize the extra resistance introduced by the copper tracks. 25 vpos positive supply 26 cvcc internal positive voltage supply filter. 27 agnd analog ground, must be shorted with bgnd. 28 rlim constant current feed programming pin (via rlim). rlim should be connected close to this pin and agnd pin to avoid noise injection. 29 iref internal bias current setting pin. rref should be connected close to this pin and agnd pin to avoid noise injection. 30 rth off-hook threshold programming pin (via rth). rth should be connected close to this pin and agnd pin to avoid noise injection. 31 rd dc feedback and ring trip input. rd should be connected close to this pin and agnd pin to avoid noise injection. 32 iltf transversal line current image output. 33 csvr battery supply filter capacitor. 34 bgnd battery ground, must be shorted with agnd. 35 vbat regulated battery voltage self generated by the device via dc/dc converter. must be shorted to vbat1. 37 ring 2 wire port; ring wire (ib is the current sunk into this pin). 41 tip 2 wire port; tip wire (ia is the current sourced from this pin). 43 crev reverse polarity transition time control. one proper capacitor connected between this pin and agnd is setting the reverse polarity transition time. this is the same transition time used to shape the "trapezoidal ringing" during ringing injection. 44 vbat1 frame connection. must be shorted to vbat. n pin function table 5. (continued) 5/25 STLC3055N table 6 shows how to set the different slic operating modes. table 6. slic operating modes. 3.1 dc/dc converter the dc/dc converter controller is driving an external power mos transistor (p-channel) in order to gen- erate the negative battery voltage needed for device operation. the dc/dc converter controller is synchronised with an external clk (125khz typ.)or with an internal clock generated when the pin clk is connected to cvcc. one sensing resistor in series to vpos supply allows to fix the maximum allowed input peak current. this feature is implemented in order to avoid over- load on vpos supply in case of line transient (ex. ring trip detection). the typical value is obtained for a sensing resistor equal to 110m ? that will guarantee an average current consumption from vpos < 700ma. when in on-hook the self generated battery voltage is set to a pre- defined value. this value can be adjusted via one external resistor (rf1) and it is typical -50v. when ring mode is se- lected this value is increased to -70v typ. once the line goes in off-hook condition, the dc/dc converter automatically adjust the generated battery voltage in order to feed the line with a fixed dc current (programmable via rlim) optimising in this way the power dissipation. 3.2 operating modes 3.2.1 power down when this mode is selected the slic is switched off and the tip and ring pins are in high impedance. also the line detectors are disabled therefore the off-hook condition cannot be detected. this mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. this mode is also forced by STLC3055N in case of thermal overload (t j > 140c). in this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. no ac transmission is possible in this mode. 3.2.2 high impedance feeding (hi-z) this operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. the output voltage in on-hook condition is equal to the self generated battery voltage (-50v typ). when off-hook occurs the det becomes active (low logic level). pd d0 d1 d2 operating mode 0 0 0 x power down 1 0 0 x h.i. feeding (hi-z) 1 0 1 0 active normal polarity 1 0 1 1 active reverse polarity 1 1 1 0 active ttx injection (n.p.) 1 1 1 1 active ttx injection (r.p.) 1 1 0 0/1 ring (d2 bit toggles @ fring) STLC3055N 6/25 the off-hook threshold in hi-z mode is the same value as programmed in active mode. the dc characteristic in hi-z mode is just equal to the self generated battery with 2x(1600 ? +rp) in series (see fig. 4), where rp is the external protection resistance. no ac transmission is possible in this mode. figure 4. dc characteristic in hi-z mode. 3.2.3 active 3.2.3.1 dc characteristics & supervision when this mode is selected the STLC3055N provides both dc feeding and ac transmission. the STLC3055N feeds the line with a constant current fixed by rlim (20ma to 40ma range). the on-hook voltage is typically 40v allowing on-hook transmission; the self generated vbat is -50v typ. if the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3055N behaves like a 40v voltage source with a series impedance equal to the protection resistors 2xrp (typ. 2x50 ? ). fig. 5 shows the typical dc characteristic in active mode. figure 5. dc characteristic in active mode the line status (on/off hook) is monitored by the slic?s supervision circuit. the off-hook threshold can be programmed via the external resistor rth in the range from 5ma to 9ma. independently on the programmed constant current value, the tip and ring buffers have a current source capability limited to 80ma typ. moreover the power available at vbat is controlled by the dc/dc converter that limits the peak current drawn from the vpos supply. the maximum allowed current peak is set by r sense resistor. 3.2.3.2 ac characteristics the slic provides the standard slic transmission functions: once in active mode the slic can operate with two different tx, rx gain. setting properly by the gain set vbat il vl vbat (-50v) 2x(r1+rp) slope: 2x(r1+rp) (r1=1600ohm) il ilim vl vbat (-50v) 10v 2rp (20 to 40ma) 7/25 STLC3055N control bit (see table 7). table 7. gain set in active mode input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external zac impedance. transmit and receive: the ac signal present on the 2w port (tip/ring) is transferred to the tx output with a -6db or -12db gain and from the rx input to the 2w port with a 0db or +6db gain. 2 to 4 wire conversion: the balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance za and zb once in active mode (d1=1) the slic can operate in different states setting properly d0 and d2 control bits (see also table 8). table 8. slic states in active mode 3.2.3.3 polarity reversal the d2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. this means that the tip and ring wire exchange their polarities following a ramp transition (see fig.6). the transition time is controlled by an external capacitor crev. this capacitor is also setting the shape of the ringing trapezoidal waveform. when the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (crev). figure 6. tip/ring typical transition from direct to reverse polarity 3.2.3.4 metering pulse injection (ttx) the metering pulses circuit consists of a burst shaping generator that gives a square wave shaped and a low pass filter to reduce the harmonic distortion of the output signal. the metering pulse is obtained starting from two logic signals: ckttx: is a square wave at the ttx frequency (12 or 16khz) and should be permanently applied to gain set 4 to 2 wire gain 2 to 4 wire gain impedance synthesis scale factor 0 0db -6db x 50 1 +6db -12db x 25 d0 d1 d2 operating mode 0 1 0 active normal polarity 0 1 1 active reverse polarity 1 1 0 active ttx injection (n.p.) 1 1 1 active ttx injection (r.p.) gnd tip ring dv/dt set by crev 4v typ. 40v typ on-hook STLC3055N 8/25 the ckttx pin or at least for all the duration of the ttx pulse (including rising and decay phases). d0: enable the ttx generation circuit and define the ttx pulse duration. these two signals are processed by a dedicated circuitry integrated on chip that generate the metering pulse as an amplitude modulated shaped squarewave (sqttx) (see fig.7). both the amplitude and the envelope of the squarewave (sqttx) can be programmed by means of ex- ternal components. in particular the amplitude is set by the two resistors rlv and the shaping by the ca- pacitor cs. figure 7. metering pulse generation circuit. the waveform so generated is then filtered and injected on the line. the low pass filter can be obtained using the integrated buffer op1 connected between pin fttx (op1 non inverting input) and rttx (op1 output) (see fig.7) and implementing a "sallen and key" configuration. depending on the external components count it is possible to build an optimised application depending on the distortion level required. in particular harmonic distortion levels equal to 13%, 6% and 3% can be obtained respectively with first, second and third order filters (see fig.7). the circuit showed in the "application diagram" is related to the simple first order filter. once the shaped and filtered signal is obtained at rttx buffer output it is injected on the tip/ring pins with a +6db gain or +12db gain. it should be noted that this is the nominal condition obtained in presence of ideal ttx echo cancellation (obtained via proper setting of rttx and cttx). in addition the effective level obtained on the line will depend on the line impedance and the protection re- sistors value. in the typical application (ttx line impedance =200 ? , rp = 50 ? , and ideal ttx echo cancel- lation) the metering pulse level on the line will be 1.33 or 2.66 times the level applied to the rttx pin. as already mentioned the metering pulse echo cancellation is obtained by means of two external compo- nents (rttx and cttx) that should match the line impedance at the ttx frequency. this simple network has a double effect: synthesize a low output impedance at the tip/ring pins at the ttx frequency. cut the eventual ttx echo that will be transferred from the line to the tx output. cttx1 cttx2 cs rlv rlv sqttx burst d0 ckttx shaping generator square wave pulse metering sinusoidal wave pulse metering rttx fttx low pass filter - + op1 cfl r1 r2 c2 c1 required external components vs. filter order. order cfl r1 c1 r2 c2 thd 1 x 13% 2 xxxx6% 3 xxxxx3% 9/25 STLC3055N 3.2.4 ringing when this mode is selected STLC3055N self generate an higher negative battery (-70v typ.) in order to allow a balanced ringing signal of typically 65vpeak. in this condition both the dc and ac feedback are disabled and the slic line drivers operate as voltage buffers. the ring waveform is obtained toggling the d2 control bit at the desired ring frequency. this bit in fact controls the line polarity (0=direct; 1=reverse). as in the active mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig.8). the shaping is defined by the crev external capacitor. selecting the proper capacitor value it is possible to get different crest factor values. the following table shows the crest factor values obtained with a 20hz and 25hz ring frequency and with 1ren. these value are valid either with european or usa specification figure 8. tip/ring typical ringing waveform table 9. : (*) distorsion already less than 10%. the ring trip detection is performed sensing the variation of the ac line impedance from on hook (relatively high) to off-hook (low). this particular ring trip method allows to operate without dc offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. it should be noted that such a method is optimised for operation on short loop applica- tions and may not operate properly in presence of long loop applications (> 500 ? ). once ring trip is de- tected, the det output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the d2 toggling in order to effectively disconnect the ring signal and then set the STLC3055N in the proper operating mode (normally active). 3.2.4.1 ring level in presence of more telephone in parallel as already mentioned above the maximum current that can be drawn from the vpos supply is controlled and limited via the external rsense. this will limit also the power available at the self generated negative battery. if for any reason the ringer load will be too low the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be reduced. in the typical application with r sense = 110m ? the peak current from vpos is limited to about 900ma, which correspond to an average current of 700ma max. in this condition the STLC3055N can drive up to crev crest factor @20hz crest factor @25hz 22nf 1.2 1.26 27nf 1.25 1.32 33nf 1.33 not significant (*) gnd tip ring dv/dt set by crev 2.5v typ. 65v typ. vbat 2.5v typ. STLC3055N 10/25 3ren with a ring frequency fr=25hz (1ren = 1800 ? + 1.0 f, european standard). in order to drive up to 5ren (1ren= 6930 ? + 8 f, us standard) it is necessary to modify the external components as follows: crev = 15nf rd = 2.2k ? rsense = 100m ? 3.3 layout recommendation a properly designed pcb layout is a basic issue to guarantee a correct behaviour and good noise perfor- mances. noise sources can be identified in not enough good grounds, not enough low impedance sup- plies and parasitic coupling between pcb tracks and high impedance pins of the device. particular care must be taken on the ground connection and in this case the star configuration allows sure- ly to avoid possible problems (see application diagram figg. 9 and 10). the ground of the power supply (vpos) has to be connected to the center of the star, let?s call this point supply gnd. this point should show a resistance as low as possible, that means it should be a ground plane. in particular to avoid noise problems the layout should prevent any coupling between the dc/dc convert- er components that are referred to pgnd (cvpos, cd, l) and analog pins that are referred to agnd (ex: rd, iref, rth, rlim, vf). agnd and bgnd must be shorter together. the gnd connection of protec- tion components have to be connected to the supply gdnd. as a first reccomendation the components cv, l, d1, cvpos, rsense should be kept as close as pos- sible to each other and isolated from the other components. additional improvements can be obtained: decoupling the center of the star from the analog ground of STLC3055N using small chokes. adding a capacitor in the range of 100nf between vpos and agnd in order to filter the switch frequency on vpos. 3.4 external components list in order to properly define the external components value the following system parameters have to be de- fined: the ac input impedance shown by the slic at the line terminals "zs" to which the return loss measurement is referred. it can be real (typ. 600 ? ) or complex. the ac balance impedance, it is the equivalent impedance of the line "zl" used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). it is usually a complex impedance. the value of the two protection resistors rp in series with the line termination. the line impedance at the ttx frequency "zlttx". the metering pulse level amplitude measured at line termination "vlottx". in case of low order filtering, vlottx represents the amplitude (vrms) of the fundamental frequency component. (typ 12 or 16khz). pulse metering envelope rise and decay time constant " ". the slope of the ringing waveform " ? v tr / ? t ". the value of the constant current limit current "ilim". the value of the off-hook current threshold "i th ". the value of the ring trip rectified average threshold current "i rth ". the value of the required self generated negative battery "v batr " in ring mode (max value is 70v). this value can be obtained from the desired ring peak level + 5v. the value of the maximum current peak sunk from vpos "ipk". 11/25 STLC3055N table 10. external components name function formula typ. value rrx rx input bias resistor 100k ? 5% rref bias setting current rref = 1.3/ibias ibias = 50 a 26k ? 1% csvr negative battery filter csvr = 1/(2 ? fp ? 1.8m ? ) fp = 50hz 1.5nf 10% 100v rd ring trip threshold setting resistor rd = 100/i rth 2k ? < rd < 5k ? 4.12k ? 1% @ irth = 24ma cac ac/dc split capacitance 22 f 20% 15v @ rd = 4.12k ? rp line protection resistor rp > 30 ? 50 ? 1% rlim current limiting programming rlim = 1300/ilim 32.5k ? < rlim < 65k ? 52.3k ? 1% @ ilim = 25ma rth off-hook threshold programming (active mode) rth = 290/i th 27k ? < rth < 52k ? 32.4k ? 1% @i th = 9ma crev reverse polarity transition time programming crev = ((1/3750) ? t/ ? v tr ) 22nf 10% 10v @ 12v/ms rdd pull up resistors 100k ? cvcc internally supply filter capacitor 100nf 20% 10v cvpos positive supply filter capacitor with low impedance for switch mode power supply 100 f(4) cv battery supply filter capacitor with low impedance for switch mode power supply 100 f 20% 100v (5) cvb high frequency noise filter 470nf 20% 100v crd (6) high frequency noise filter 100nf 10% 15v q1 dc/dc converter switch p ch. mos transistor rds(on) 1.2 ? ,vds = -100v total gate charge=20nc max. with vgs=4.5v and vds=1v id>500ma possible choiches: irf9510 or irf9520 or irf9120 or equivalent d1 dc/dc converter series diode v r > 100v, t rr 50ns smbyw01-200 or equivalent rsense dc/dc converter peak current limiting r sense = 100mv/i pk 110m ? @i pk = 900ma rf1 negative battery programming level 250k ? 13/25 STLC3055N figure 9. application diagram. figure 10. application diagram without metering pulse generation. zac rs rrx za zb ccomp tx zac1 zac zb tx control interface d0 gain set d1 d2 bgnd cvcc cac cac iref rref gate vbat p-ch q1 rf1 clk crev crev d00tl489a csvr STLC3055N d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cs cfl rlv rlv ttx clock cttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx rttx system gnd agnd bgnd suggested ground lay-out vdd cvb crd pgnd pd pd zac rs za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref gate vbat p-ch q1 rf1 clk crev crev d00tl490/b csvr STLC3055N d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx system gnd agnd bgnd suggested ground lay-out vdd cvb crd pgnd gain set pd pd rrx STLC3055N 14/25 4 electrical characteristics test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the oper- ating range: -40 to +85c. symbol parameter test condition min. typ. max. unit dc characteristics v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = 0 to 85c 44 50 v v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = -40 to 85c 42 48 v v loa line voltage il = 0, active t amb = 0 to 85c 33 40 v v loa line voltage il = 0, active t amb = -40 to 85c 31 37 v ilim lim. current programming range active mode 20 40 ma ilima lim. current accuracy active mode. rel. to programmed value 20ma to 40ma -10 10 % rfeed hi feeding resistance hi-z (high impedance feeding) 2.4 3.6 k ? ac characteristics l/t long. to transv. (see appendix for test circuit) rp = 50 ? , 1% tol., active n. p., r l = 600 ? (*) f = 300 to 3400hz 50 58 db t/l transv. to long. (see appendix for test circuit) rp = 50 ? , 1% tol., active n. p., r l = 600 ? (*) f = 300 to 3400hz 40 45 db t/l transv. to long. (see appendix for test circuit) rp = 50 ? , 1% tol., active n. p., r l = 600 ? (*) f = 1khz 48 53 db 2wrl 2w return loss 300 to 3400hz, active n. p., r l = 600 ? (*) 22 26 db thl trans-hybrid loss 300 to 3400hz, 20log|vrx/vtx|, active n. p., r l = 600 ? (*) 30 db ovl 2w overload level at line terminals on ref. imped. active n. p., r l = 600 ? (*) 3.2 dbm txoff tx output offset active n. p., r l = 600 ? (*) -250 250 mv g24 transmit gain abs. 0dbm @ 1020hz, active n. p., r l = 600 ? (*) -6.4 -5.6 db g42 receive gain abs. 0dbm @ 1020hz, active n. p., r l = 600 ? (*) -0.4 0.4 db 15/25 STLC3055N g24f tx gain variation vs. freq. rel. 1020hz; 0dbm, 300 to 3400hz, active n. p., r l = 600 ? (*) -0.12 0.12 db g24f rx gain variation vs. freq. rel. 1020hz; 0dbm, 300 to 3400hz, active n. p., r l = 600 ? (*) -0.12 0.12 db v2wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 ? (*) t amb = 0 to +85c -73 -68 dbmp v2wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 ? (*) t amb = -40 to +85c -68 dbmp v4wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 ? (*) t amb = 0 to +85c -75 -70 dbmp v4wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 ? (*) t amb = -40 to +85c -75 dbmp thd total harmonic distortion active n. p., r l = 600 ? (*) -44 db vttx metering pulse level on line active - ttx; gain set = 1 zl = 200 ? fttx = 12khz; 260 340 mvrms clkfreq clk operating range -10% 125 10% khz (*) r l : line resistance ring vring line voltage ring d2 toggling @ fr = 25hz load = 3ren; crest factor = 1.25 1ren = 1800 ? + 1.0 f t amb = 0 to +85c 45 49 vrms vring line voltage ring d2 toggling @ fr = 25hz load = 3ren; crest factor = 1.25 1ren = 1800 ? + 1.0 f t amb = -40 to +85c 44 48 vrms detectors iofftha off/hook current threshold act. mode, rth = 32.4k ? 1% (prog. ith = 9ma) 10.5 ma roftha off/hook loop resistance threshold act. mode, rth = 32.4k ? 1% (prog. ith = 9ma) 3.4 k ? iontha on/hook current threshold act. mode, rth = 32.4k ? 1% (prog. ith = 9ma) 6ma 4 electrical characteristics test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the oper- ating range: -40 to +85c. symbol parameter test condition min. typ. max. unit STLC3055N 16/25 rontha on/hook loop resistance threshold act. mode, rth = 32.4k ? 1% (prog. ith = 9ma) 8k ? ioffthi off/hook current threshold hi z mode, rth = 32.4k ? 1% (prog. ith = 9ma) 10.5 ma roffthi off/hook loop resistance threshold hi z mode, rth = 32.4k ? 1% (prog. ith = 9ma) 800 ? ionthi on/hook current threshold hi z mode, rth = 32.4k ? 1% (prog. ith = 9ma) 6ma ronthi on/hook loop resistance threshold hi z mode, rth = 32.4k ? 1% (prog. ith = 9ma) 8k ? irt ring trip detector threshold range ring 20 50 ma irta ring trip detector threshold accuracy ring -15 15 % trtd ring trip detection time ring tbd ms td dialling distortion active -1 1 ms rlrt (1) loop resistance 500 ? thal tj for th. alarm activation 160 c (1) rlrt = maximum loop resistance (incl. telephone) for correct ring trip detection. digital interface inputs: d0, d1, d2, pd, clk outputs: det vih in put high voltage 2 v vil input low voltage 0.8 v iih input high current -10 10 a iil input low current -10 10 a vol output low voltage iol = 1ma 0.45 v psrr and power consumption pserrc power supply rejection vpos to 2w port vripple = 100mvrms 50 to 4000hz 26 36 db ivpos vpos supply current @ ii = 0 hi-z on-hook active on-hook, ring (line open) 13 50 55 25 80 90 ma ma ma ipk peak current limiting accuracy ring off-hook rsense = 110m ? -20% 950 +20% mapk 4 electrical characteristics test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the oper- ating range: -40 to +85c. symbol parameter test condition min. typ. max. unit 17/25 STLC3055N 5 appendix a 5.1 STLC3055N test circuits referring to the application diagram shown in fig. 9 of the STLC3055N datasheet and using as external components the typ. values specified in the "external components" tables 10 and 11 (pages 11, 12) find below the proper configuration for each measurement. all measurements requiring dc current termination should be performed using "wandel & goltermann dc loop holding circuit gh-1" or equivalent. figure 11. 2w return loss 2wrl = 20log(|zref + zs|/|zref-zs|) = 20log(e/2vs) figure 12. thl trans hybrid loss thl = 20log|vrx/vtx| tip ring rx tx STLC3055N application circuit w&g gh1 zref e vs 1kohm 1kohm 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm 100 f tip ring rx tx STLC3055N application circuit w&g gh1 vrx vtx 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm STLC3055N 18/25 figure 13. g24 transmit gain g24 = 20log|2vtx/e| figure 14. g42 receive gain g42 = 20log|vi/vrx| figure 15. psrrc power supply rejection vpos to 2w port pssrc = 20log|vn/vl| tip ring rx tx STLC3055N application circuit w&g gh1 e vtx 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm tip ring rx tx STLC3055N application circuit w&g gh1 vrx vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm tip ring rx tx STLC3055N application circuit w&g gh1 vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm vn vpos ~ 19/25 STLC3055N figure 16. l/t longitudinal to transversal conversion l/t = 20log|vcm/vl| figure 17. t/l transversal to longitudinal conversion t/l = 20log|vrx/vcm| figure 18. vttx metering pulse level on line tip ring rx tx STLC3055N application circuit w&g gh1 vcm vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 f 300ohm 100 f impedance matching better than 0.1% 600ohm tip ring rx tx STLC3055N application circuit vcm w&g gh1 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 f 300ohm 100 f impedance matching better than 0.1% vrx tip ring rx tx STLC3055N application circuit fttx (12 or 16khz) vlttx 200ohm ckttx STLC3055N 20/25 figure 19. v2wp and w4wp: idle channel psophometric noise at line and tx. v2wp = 20log|vl/0.774l|; v4wp = 20log|vtx/0.774l| 6 appendix b 6.1 STLC3055N overvoltage protection figure 20. simplified configuration for indoor overvoltage protection figure 21. standard overvoltage protection configuration for k20 compliance tip ring rx tx STLC3055N application circuit w&g gh1 vl psophometric filtered 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm vtx psophometric filtered tip ring bgnd vbat rp1 rp2 rp1 rp2 2 x sm6t39a STLC3055N tip ring rp1 = 30ohm: rp2 =fuse or ptc > 18ohm stpr120a stpr120a tip bgnd vbat rp1 rp2 rp1 = 30ohm: rp2 =fuse or ptc > 18ohm 2 x sm6t39a STLC3055N tip ring rp1 rp2 ring lcp1521 21/25 STLC3055N 7 appendix c 7.1 typical state diagram for STLC3055N operation figure 22. tj>tth pd=0, d0=d1=0 pd=1, d0=d1=0 power down hi-z feeding off hook detection active off hook on hook detection for t>tref active on hook ringing ring burst d0=1, d1=0, d2=0/1 ring trip detection normally used for on hook transmission ring pause d0=0, d1=1, d2=0 ring burst off hook detection d0=0, d1=1, d2=0 on hook condition note: all state transitions are under the microprocessor control. STLC3055N 22/25 8 appendix d 8.1 stlc3055q STLC3055N compatibility. STLC3055N is pin to pin compatible with the old stlc3055q but offer a better performance in term of power consumption and can be set in a new gain configuration in order to be compatible with the 3.3v codec. 8.1.1 typical power consumption comparison table 13. to meet this result some differences, with a minimum impact on the application, has been introduced in STLC3055N. 8.1.2 hardware difference: rx input. in STLC3055N it is necessary a 100k ? external resistor between rx input and agnd to bias the input stage. rp. the STLC3055N required a rp value of 50 ? instead of 41 ? . ttx filter. to optimize the ttx signal dynamic we have change the values of rlv and cfl; table 14. 8.1.3 parameter differences: table 15. operative mode stlc3055q STLC3055N hi-z 52 - 60ma 13 - 25ma active on hook 93 - 115ma 50 - 80ma ring (no ren) 120 - 140ma 55 - 90ma component stlc3055q STLC3055N rrx 100k ? rp 41 ? 50 ? rlv 27k ? 16.2k ? cfl 1nf 1.5nf parameter stlc3055q STLC3055N absolute max. rating 17v 13v operating range 15.8v 12v typ metering pulse level (gs 1) 340mvrms typ metering pulse level (gs 0) 200mvrms 170mvrms 23/25 STLC3055N 9 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 23. tqfp44 (10 x 10) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 e 0.80 0.031 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?(min.), 3.5?(typ.), 7?(max.) tqfp44 (10 x 10 x 1.4mm) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 0076922 d STLC3055N 24/25 table 16. revision history date revision description of changes september 2003 4 first issue october 2004 5 update functional description and electrical characteristics. aligned the graphic style to be compliant with the new ?corporate technical pubblications design guide? october 2004 6 modified the application diagrams and some typo errors. november 2004 7 removed all max. values of the ?line voltage? parameter on the page 14/24. changed the unit from ma to % of the ?ilima? parameter on the page 14/ 24. january 2005 8 add pin 4 pd in applications and block diagram add in table 2 ?esd rating? july 2005 9 changed vttx value february 2006 10 added part number ?e-STLC3055N? (ecopack). added rrx resistance in the figures 9 and 10. added appendix d. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 25/25 STLC3055N |
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